1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an improved semiconductor memory device having bit lines for inputting and outputting data for memory cells.
2. Description of the Prior Art
FIG. 45 is a block diagram illustrating an example of a conventional static RAM (referred to as "SRAM" hereinafter). In FIG. 45, a row address input terminal group 1 receives external row address data, and the inputted row address data is amplified or inverted by a row address buffer 2 and is applied to a row decoder 3. The row decoder 3 decodes the row address data applied through the input terminal group 1.
On the other hand, a column address input terminal group 4 receives external column address data, and the inputted column address data is amplified or inverted by a column address buffer 5 and is applied to a column decoder 6. The column decoder decodes the column address data applied through the input terminal group 4. A memory cell array 7 includes a plurality of memory cells arranged in a matrix, for storing information. A read voltage of a small amplitude read from the memory cell array 7 is applied through a multiplexer 8 to a sense amplifier 9 to be amplified therein. An output from the sense amplifier 9 is further amplified by an output data buffer 10 to a level required for fetching it externally from the semiconductor memory device, and is externally outputted through a read data output terminal 11.
A write data input terminal 12 receives write data. The write data thus applied is amplified by an input data buffer 13. A chip selection signal is applied to a terminal 14, and a read/write control signal is applied to a terminal 15. A read/write control circuit 16 controls the sense amplifier 9, output data buffer 10 and input data buffer 13 in accordance with selection/non-selection of the chip and read/write modes of the data, which are determined by the chip selection signal and the read/write control signals, respectively.
FIG. 46 shows peripheral structures of the memory cell array 7 in the SRAM shown in FIG. 45. In FIG. 46, for simplicity reasons, the memory cell array 7 is shown in a form of two rows by two columns. Referring to FIG. 46, memory cells 24a-24d are disposed at crossings of a bit line pair 20a and 20b and a bit line pair 21a and 21b, and word lines 22 and 23 connected to output terminals of the row decoder 3, respectively. Bit line loads 25a, 25b, 26a and 26b are disposed at ends of the bit lines 20a, 20b, 21a and 21b, respectively. These bit line loads 25a, 25a, 26a and 26b are formed of transistors which have first conductive terminals and gates connected to a power supply 18 and second conductive terminals connected to the corresponding bit lines.
The multiplexer 8 shown in FIG. 45 includes transfer gates 27a, 27b, 28a and 28b which are disposed at the other end of each of the bit lines 20a, 20b, 21a and 21b, respectively. Each of the transfer gates has a gate to which an output signal from the column decoder 6 shown in FIG. 45 is applied, its drain/source connected to a corresponding bit line and its source/drain connected to a corresponding input/output (IO) line of an IO line pair 29a and 29b. A potential difference between the IO lines 29a and 29b is sensed by the sense amplifier 9. An output from the sense amplifier 9 is amplified by the output buffer 10.
Each memory cell 24 in FIG. 46 may be in a form of a MOS memory cell of a high resistance load type shown in FIG. 47 or a CMOS memory cell shown in FIG. 48.
The memory cell shown in FIG. 47 includes driver transistors 41a and 41b. The transistor 41a has its drain connected to a memory node 45a, its gate connected to a storage node 45b and its source grounded. The transistor 41b has its drain connected to a storage node 45b, its gate connected to a storage node 45a and its source grounded. The memory cell 24 further includes access transistors 42a and 42b. The transistor 42a has its drain or source connected to the storage node 45a, its gate connected to a word line 22 or 23 and its source or drain connected to a bit line 20a or 21a. The transistor 42b has its drain or source connected to the storage node 45b, its gate connected to a word line 22 or 23 and its source or drain connected to a bit line 20b or 21b. The memory cell 24 also includes load resistances 43a and 43b, which are connected at ends to the power supply 18 and at other ends to the storage nodes 45a and 45b, respectively.
The memory cell 24 shown in FIG. 48 includes p channel transistors 44a and 44b in place of the load resistances 43a and 43b in the memory cell 24 shown in FIG. 47. The transistor 44a has its drain connected to the storage node 45a, its gate connected to the storage node 45b and its source connected to the power supply 18. The transistor 44b has its drain connected to the storage node 45b, a gate connected to the storage node 45a and its source connected to the power supply 18.
The conventional semiconductor memory device shown in FIGS. 45, 46, 47 and 48 operates as follows. It is assumed that the memory cell 24a is to be selected in the memory cell array 7. In this case, the row address input terminal group 1 applies a row address signal, which corresponds to a row connected to the memory cell 24a to be selected, through the row address buffer 2 to the row decoder 3. Thereby, the row decoder 3 sets the word line 22 connected to the memory cell 24a at a selection level (e.g., "H" level), and also sets the other word line 23 at a non-selection level (e.g., "L" level).
On the other hand, the column address input terminal group 4 applies a column address signal, which selects a column corresponding to the bit line pair 20a and 20b connected to the memory cell 24a to be selected, through the column address buffer 5 to the column decoder 6. Thereby, the column decoder 6 makes only the transfer gates 27a and 27b connected to the bit line pair 20a and 20b conductive. Consequently, only the selected bit lines 20a and 20b are connected to the IO lines 29a and 29b, while the unselected bit line pair 21a and 21b is isolated from the IO line pair 29a and 29b.
Read operations of the selected memory cell 24a will now be described below. It is assumed that the storage node 45a of the memory cell 24a is at the "H" level and the storage node 45b is at the "L" level. In this case, one of the driver transistor 41a in the memory cell is non-conductive, and the other driver transistor 41b is conductive. Further, the word line 22 is at the "H" level and thus in the selected state, so that both the access transistors 42a and 42b in the memory cell 24a are conductive. Therefore, a direct current flows from the power supply 18 through the bit line load 25b, bit line 20b, access transistor 42b and driver transistor 41b to the ground.
However, the direct current does not flow through the other path, i.e., from the power supply 18 through the bit line load 20a, bit line 20a, access transistor 42a and driver transistor 41a to the ground, because the driver transistor 41a is not conductive. In this operation, the potential in the bit line 20a through which the direct current does not flow has a value of (supply potential-Vth), in which "Vth" is a threshold voltage of the bit line load transistors 25a, 25b, 26a and 26b.
The potential of the bit line 20b through which the direct current flows has a value of (supply potential-Vth-.DELTA.V) which is reduced by .DELTA.V from (supply potential-Vth), because the power-supply voltage is divided by the conductive resistance of the driver transistor 41b, access transistor 42b and of the bit line load 25b. In the above term, .DELTA.V is called a bit line amplitude, and is generally of a value from 50 mV to 500 mV which is adjusted in accordance with a value of the bit line load.
This bit line amplitude appears on the IO lines 29a and 29b through the conductive transfer gates 27a and 27b, and is amplified by the sense amplifier 9. The output from the sense amplifier 9 is amplified by the output buffer 10 and is read as the data output from the output terminal 11. In the reading operation, the input data buffer 13 is controlled not to drive the IO line pair 29a and 29b by the read/write control circuit 16.
In the writing operation, the potential of the bit line for writing the data at the "L" level is forced to a low potential, and the potential of the other bit line is raised to a high potential, whereby the data is written in the memory cell. For example, in order to write an inverted data in the memory cell 24a, the data input buffer 13 sets the IO line 29a at the "L" level and also sets the other IO line 29b at the "H" level, so that the bit line 20a is set at the "L" level and the other bit line 20b is set at the "H" level, whereby the data is written.
FIG. 49 is a circuit diagram illustrating the sense amplifier and the IO line driver circuit. Referring to FIG. 49, n-channel MOSFETs 59 and 60 form a differential input circuit, and have gates to which differential input signals Vin and /Vin are applied, respectively. Sources of the n-channel MOSFETs 59 and 60 are commonly connected and grounded through a n-channel MOSFET 61 for power down. This n-channel MOSFET 61 becomes conductive in response to a chip enable signal (CE) applied to an input terminal 62. Drains of the n-channel MOSFETs 59 and 60 are connected to drains of p-channel MOSFETs 57 and 58 which form a current mirror circuit. The p-channel MOSFETs 57 and 58 have sources connected to the power supply Vcc and gates which are commonly connected. An amplified output is obtained through an output terminal 63 from a node of the n-channel MOSFET 60 and the p-channel MOSFET 58.
The IO line load circuit 50 includes n-channel MOSFETs 55 and 56, sources of which are connected to a pair of the IO lines 29a and 29b forming active loads. These IO lines 29a and 29b are connected through terminals 51 and 52 to the sources of the transfer gates 27a and 28b and the sources of the transfer gates 27b and 28b, respectively. The respective gates and drains of the n-channel MOSFETs 55 and 56 are commonly connected to the power supply Vcc.
As described above, in the semiconductor memory device such as a SRAM, at a periphery of the memory cell array, various circuits (bit line loads, multiplexer, column decoder, sense amplifier, and the like) which are associated to the bit lines are provided. These circuits which are directly associated to the bit lines will be called generally as bit line peripheral circuits hereinafter.
In the conventional semiconductor memory device, the bit lines and the bit line peripheral circuits can be coupled together only at upper and lower terminating ends of the bit lines. Therefore, most of the bit line peripheral circuits are concentrated at the vicinity of the upper and lower ends of the bit lines. This can also be understood from a layout structure of a SRAM chip disclosed in articles "A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization" (IEEE Journal of Solid-State Circuits, Vol.23, No.5, October 1988) and "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon" (IEEE Journal of Solid-State Circuits, Vol.22, No.5, October 1987). Therefore, the sizes of the bit line peripheral circuits in the conventional semiconductor memory device largely depend on the bit line pitch. That is, if the bit line pitch is large, it is possible to arrange bit line peripheral circuits having large structures or large driving capacities, (bit line peripheral circuits having transistors of large channel lengths and/or channel widths, and/or many transistors). However, if the bit line pitch is small, only bit line peripheral circuits having small structures or small driving capacities can be arranged. The bit line pitch is determined by the sizes of the memory cells, and has been progressively reduced due to the progress of the high integration technique in recent years. Accordingly, it is impossible in the conventional semiconductor memory device to arrange the bit line peripheral circuits having large areas, and thus it is difficult to obtain an intended performance. For example, a device having a redundancy circuit, of which a program fuse is arranged for every column can be reduced in size only to a restricted extent due to a device for cutting off the fuses, even if reduction of the memory sizes can be achieved owing to the development of the processing technique. Therefore, it is impossible to arrange the fuses for respective columns, and thus the memory sizes can be reduced only to a restricted extent, so that the chip size cannot be sufficiently reduced.
The above problem is caused not only in the SRAMs but also in dynamic RAMs (will be call as "DRAM" hereinafter) and others.